The present invention relates to a system having a PLL (phase lock loop) circuit, and to techniques effectively applicable to a system including a semiconductor integrated circuit device such as a CMOS gate array in which a clock signal is generated by a PLL circuit and which includes a logic circuit operating in accordance with the clock signal.
Logic circuits which operate in synchronism with a clock signal. A circuit for generating a clock signal have been known is disclosed in "IEEE Journal of Solid-State Circuits", Vol. SC-22, No. 2 (1987), pp. 255-261. Besides, PLL circuits are disclosed in, for example, Japanese Patent Applications Laid-open No. 284014/1993 and No. 315948/1993.